In general, a flash memory is one kind of PROM (programmable read only memory) which enables data to be electrically rewritten. The flash memory corresponds to a nonvolatile memory whose data is not lost even when power is turned off.
Based on cell-array architecture, flash memory may have a NOR-type structure where cells are arranged in parallel between a bit line and a ground. Flash memory may also have a NAND-type structure where cells are arranged in series. The NOR-type flash memory has a parallel structure and may be used for booting a mobile phone since it provides relatively high-speed random access reading operations. The NAND-type flash memory provides relatively lower reading speeds, but relatively higher writing speeds. In this respect, the NAND-type flash memory may be more appropriate for data storage. It may also be capable of a greater degree of miniaturization.
Flash memory may be classified into as stack gate type or split gate type on the basis of the unit cell structure. Based on the type of charge storage layer used, the flash memory may also be classified as a floating gate device or a silicon-oxide-nitride-oxide-silicon (SONOS) device. The floating gate device includes a floating gate which may be formed by polysilicon covered with an insulator. Charges may be injected to or discharged from the floating gate by a channel hot carrier injector or F-N (Fowler-Nordheim) tunneling, so that data is stored in and erased from the floating gate.
A method of manufacturing the NOR-type floating gate device may include controlling a cell threshold voltage by forming a stack gate, including a floating gate, an insulation layer between gates (for example, Oxide-Nitride-Oxide ONO layer), and a control gate. An SAS (Self-Aligned Source) process may be used to form a common source line.
An SAS process may be performed to decrease a cell dimension along the direction of a word line. In an SAS process, a field oxide layer is etched at an etching selection ratio of a polysilicon layer for a gate electrode, a silicon substrate and a field oxide layer, and then impurity ions are implanted thereto, thereby forming the common source line.
Referring to FIGS. 1A to 1C, SAS process according to the related art will be briefly explained. In FIG. 1A, a stack gate 20 is formed including a tunnel oxide layer 22, a floating gate 24, a gate dielectric layer 26 and a control gate 28. Through the SAS process, a source region for 8 to 16 bit cell is opened, and an oxide layer is removed from a device isolation region. The oxide layer formed in the device isolation region corresponds to a field oxide layer formed by STI (Shallow Trench Isolation). By removing the oxide layer, a trench 14 is formed in a common source region, which is a region for a common source line exposed between each stack gate 20.
Then, dopant ions (As or P) are implanted into the surface of the exposed substrate, forming an ion-implantation layer. The ion implantation layer serves as the common source line 11, 12, which electrically connects source diffusion regions of respective cells.
FIG. 1B is a cross sectional view illustrating dopant diffused in the common source region according to the related art. Due to the trench 14 formed by the SAS process, the substrate 10 has an uneven surface.
However, in semiconductor device processes below 0.13 μm, if dopant (As or P) ions are implanted using the SAS process, dopant out-diffusion occurs in the lateral common source line 11. There is a loss of dopant, making it difficult to lower a resistance value (Rs) in the common source line.